zboszor wrote:I used 7MHz and "#7FFD span: 1024K" all the time. The "Cache: ON/OFF" setting makes the difference.
pentevo: int signal length corrected for extensive wait states: while wait_n==0, int length counter doesn't count
zboszor wrote:This bug feels like a problem with DMA versus cache
zboszor wrote:or a lost interrupt
zboszor wrote:When was the last time Base+TSConf took a snapshot from Baseconf?
TS-Labs wrote:zboszor wrote:This bug feels like a problem with DMA versus cache
Such a bug is possible due to lack of updating cached data being overwritten in DRAM by DMA. But such a bug is 100% deterministic and cannot be spontaneous. So this is not the case.
TS-Labs wrote:zboszor wrote:or a lost interrupt
INT can't be lost during DMA, ~WAIT is only formed at GLUclock or RS-232 addressing.
TS-Labs wrote:zboszor wrote:When was the last time Base+TSConf took a snapshot from Baseconf?
Well, mr. Noah made the last code merge right before he loaded his Ark. I'll merge it today.
zboszor wrote:What about 14MHz? It's supposed to have extended wait states
zboszor wrote:and the description of r651 from the pentevo SVN looks exactly like that.
zboszor wrote:The interrupt signal length problem may trigger this problem if the CPU is stressed.
zboszor wrote:How about a test firmware for Base+TSconf with the same interrupt length fix applied to the TSconf side?
zboszor wrote:Or do we get it automatically after the merge?
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